Test feature extraction and complete test plan creation w.r.t to achieving 100 % coverage goals

Functional coverage matrix to get maximum cross-functional verification

Complete Verification Environment built up from scratch and flow setup

Matlab and reference model integration and checks

Good experience in power architecture and power reduction techniques.

UPF flow setup

GLS flow setup with different tools and debug.

X propagation clean up and debug

Gate Level Simulation sign-off

Expertise in the setup of palladium, Zebu and FPGA verification environment

Experienced in designing Used and Application scenarios on such platforms

Performance and Benchmarking

Help the SW and compiler or debug team to qualify the SW

Boot code validation or development

Experience in delivering multiple SoC and expertise in System Architecture to take ownership of SoC verification.

Expertise in various processors as Cortex M/R series and ARM , ARC etc.

Experienced in various complex IP’s such as USB, PCIE, Ethernet , Graphics and Camera subsystem to help deliver quality

verification and debug on time.

Experience in Power architecture and UPF flow setup and simulation.

Expertise in different safety standards to help verification and certification of safety application specific SoC’s

Expertise in Analog Mixed Signal Verification Methodology

Cross-domain metric-driven verification (MDA) of analog components

Event-driven time domain behavioral modeling using AMS

Verification of the multi-million gate SoC, targeted for IoT applications having modem subsystem, multi-core subsystem was successfully done. The milestones of verification, GLS, PAGLS , coverage were met on time for tape-out. This SoC had various complex subsystems viz Modem, Memory Subsystem having NAND and DDR5 controller, and high-speed IPs such as PCIE and Ethernet .

Tool Migration – Migration of complete flow and verification setup to different EDA tools.

Methodology Migration – Complete migration of environment and setup for different flow and methodologies. Our competencies lie in environments which are build using SV, OVM, UVM, VERA, Specman.

Emulation Platform – We closely work on verification of boot code, debugger, compiler etc in parallel with debug teams. We completely perform end to end pre and post-silicon validation and verification on different emulation platforms viz Zebu, Palladium, and FPGA.

Reference Model Design and verification – SkandySys has expertise in C model creation and scoreboard development using different reference models such as:

• System C models
• Matlab reference models

First pass silicon success of an SoC was achieved by owning complete verification of the project in turnkey mode. The product was successfully demonstrated at the CES conference by the client.

Complex IPs used in the modem designs were verified with a complete environment setup and test-bench flow setup from scratch.

Close interactions with system architects were done for the development of reference models and integration of the same in the verification environment.

100% coverage goals of the complex matrix were achieved for functional coverage and code coverage.

Complete verification setup of multicore SoC which had multiple DSP, Security and processor cores was also developed from scratch.

PAGLS and GLS flow were set up for multiple clients for their many SoC environments. It was ensured that a smooth and reliable final sign off was achieved.