Experience: 2-8 yrs
- Should be very strong in Synthesis & Timing concepts
- Should have knowledge of DC-topo, RTL Compiler or talus
- Should have handled both block and top level.
- Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm
- Should have done both pre and post layout STA Flow, Timing Closure, LEC, constraint defining