RTL Design

Experience: 4-10 yrs

Location: Bangalore

Job Overview:

  1. Hands-on in Verilog/ VHDL
  2. Hands-on in Perl/ Unix scripting
  3. Hands on in SoC level RTL integration
  4. Hands on in Clock Domain Crossing (CDC) checks, Linting, equivalence checks
  5. Experience in Digital module micro-architecture and design
  6. Experience in basic RTL simulation
  7. IP generation enhancement kind of work
  8. Good knowledge of Synthesis, STA and DFT aware design.
  9. Good knowledge of ARM subsystem, I2C protocol, AMBA bus
  10. Understanding of Power Domains and low power design techniques
  11. Familiar with DSP subsystems and high speed interfaces(e.g. SERDES, GigE, 10GE)
  12. Ability to lead & motivate a team of Engineers
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